A memory system includes a memory controller connected to one or more memory components via an address/command bus and a data bus. The memory controller sends commands over the address/command bus to control which memory component writes to and/or reads from a memory space represented by data stored on the memory components. Data to be written to one of the memory components is transferred from the memory controller to a corresponding one of the memory components over the data bus, while memory to be read is transferred from a corresponding one of the memory components over the data bus to the memory controller.
Some existing memory architectures use multi-drop connections from the memory controller to the memory components. A multi-drop connection includes a trace from the memory component that branches to the memory components. This branching of the trace creates signal reflections, which frustrates high frequency operation and accordingly limits throughput between the memory controller and the memory components.
Other issues of existing memory architectures are related to capacity. The storage capacity of a memory system is limited by many factors, including the system's word width. A word is typically equal to the bit width of the data bus extending from the memory controller.
Although extending word width can lead to larger capacities, e.g. a sixty four bit system can generally have greater memory capacity than a thirty two bit system, there are many tradeoffs. As word width is increased, routing the widened data buses becomes increasingly difficult. The complex data bus routing can result in data misalignment, where bits on each link of the data bus arrive at a component at different times. This data misalignment further frustrates high frequency operation, which again affects throughput between the memory controller and the memory components. Another tradeoff for increasing word width is the increased pin count, which greatly adds to the cost of manufacturing memory controllers and memory components.
Fully Buffered Dual In-Line Memory Modules (FB-DIMMs) partially address some of the limitations discussed above. Point-to-point connections from the memory controller to an Advanced Memory Buffer (AMB) replace the multi-drop connections. A serial interface from the memory controller to the AMB reduces pin count on the memory controller and simplifies some bus routing. Each memory component contributes its portion of the entire word width.
The FB-DIMM systems introduce their own problems, however. For example, the memory controller cannot write directly to the memory components and must first write to the AMB, which generally increases cost and design complexity. Furthermore, the AMB hinders high speed operation because the process of buffering by the AMB, followed by subsequent analysis and re-sending according to a queue, introduces latency.
Yet another issue with some existing memory systems, is that the memory controller must have a data width matching the data width of each memory component. For example, a one hundred and forty four bit memory controller is compatible with one hundred and forty four bit memory, which means that the data pin count of the memory controller matches the data pin count of each memory component. As a result, device manufacturers must obtain memory components matched to the memory controller, and a high pin count on the memory controller means a high pin count for each memory component.